Semtech adds jitter attenuating and clock multiplying IC to SETS product line

April 12, 2005 Camarillo, CA -- Semtech, a supplier of analog and mixed-signal semiconductors for communications, portable devices, computers, and industrial equipment, has introduced its ACS8942A, a jitter attenuating and multiplying (JAM) phase-locked loop (PLL) for generating ultra-low jitter output clocks for SONET and SDH network equipment.

The ACS8942A adds to the company's synchronous equipment timing source (SETS) product family. According to the company, the IC features jitter generation as low as 0.10 picosecond (ps) RMS (G.813, STM-16, 1 MHz to 20 MHz band) and 0.93 ps RMS (GR-253, OC-48, 12 kHz to 20 MHz band), well below the jitter requirements of ITU-T and Telcordia specifications for up to OC-48/STM-16 systems. The company says the device dejitters the output of a line card protection device or line card clock synthesizer, providing a clock-cleaning solution for DSL access multiplexers and metropolitan or edge networking equipment with very tight jitter budgets.

With a 5mm x 5mm QFN 32-pin package, the device can be used to attenuate jitter in the network element at the point-of-use, according to the company. The IC features an integrated voltage controlled oscillator, which the company says saves cost and board space, while also eliminating long-term center frequency drift and the potential for mechanical failure of an external oscillator.

"The ACS8942A offers a significant advantage to the designer who is finding that jitter is impacting a high-speed design," contends Stewart Kelly, director of Semtech's Advanced Communications Products Division.

The device nominally inputs a 155.52 MHz reference clock using a single, differential LVPECL input, and can be configured to provide either 622.08 MHz or 77.76 MHz on a single, differential CML output. The IC features an external feedback-operating mode that allows it to input other common SONET/SDH spot frequencies (19.44, 38.88, 77.76 MHz), and allows the final output signal from any external buffers and dividers to be in exact phase alignment with the clock input.

Engineering samples of the device are now available.