JANUARY 20, 2009 -- Inphi Corp. has introduced a 28G bit-error ratio (BER) receiver reference design. The reference design will be highlighted in Inphi's booth # 2-57 at the Fiber Optics Expo in Tokyo, Japan, January 21-23.
The 28G BER Receiver is for R&D or production testing of emerging high-speed protocols from 13 to 28 Gbps, including 100-Gigabit Ethernet, 40G differential quadrature phase-shift keying (DQPSK), 14G Fibre Channel, and 100G dual-polarization quadrature phase-shift keying (DP-QPSK). The reference design is intended to accelerate time-to-market for test & measurement vendors designing next-generation 28G test platforms.
The Inphi 28G BER Receiver reference design addresses the challenge of designing a high-speed front-end at 28 Gbps, says the company; it integrates an Inphi chipset in a proven, high performance, and reliable design. The reference design, together with a 12.5G BERT and a 28G high-speed test pattern generator, create a complete 28-Gbps test system, says Inphi.
For test applications requiring clock recovery, the 28G BER Receiver reference design provides a buffered copy of the high-speed input data stream, which can be supplied to an optional clock recovery unit to generate a recovered clock. The 28G BER Receiver reference design is based on an Inphi chipset that includes a 5081DX 50-Gbps 1:4 demultiplexer, 25717CF 25-Gbps 1:2 fanout, and 20709SE 20-Gbps 2:1 selector.
"Inphi's 28G BER Receiver reference design is a simple and cost-effective tool for the development and testing of emerging higher speed interfaces," said Mark Donovan, vice president of optical assemblies for Finisar Corp. "This reference design enables us to improve our test capabilities while leveraging existing investments in 12.5G BERT systems and software."
The Inphi 28G BER Receiver reference design is available immediately.