K-micro, Anritsu collaborate on 10G EPON chip testing

DECEMBER 9, 2009 -- ASIC company K-micro (Kawasaki Microelectronics America) and Anritsu say they have developed the first test tool and methodology to analyze 10-Gbps Ethernet Passive Optical Network (EPON) chips.

DECEMBER 9, 2009 -- ASIC company K-micro (Kawasaki Microelectronics America) and Anritsu say they have developed the first test tool and methodology to analyze 10-Gbps Ethernet Passive Optical Network (EPON) chips. The successful test of K-micro’s CTXL1 10G EPON SerDes chip using Anritsu’s MP1800A Signal Quality Analyzer paves the way for 10G EPON systems to be shipped, the companies assert.

Resulting measurements of K-micro’s CTXL1 10G EPON SerDes chip demonstrate a burst mode lock time of 20 nsec, the chip maker says. “We have worked with Anritsu, a company well-respected for its technology test solutions, to develop testing for FTTH EPON chips because our customers are ready to implement EPON applications and need to know that the chips meet the specifications for the products,” said Vijay Pathak, CTO at K-micro.

The companies say there are two major challenges to evaluate 10G EPON optical line termination (OLT) burst mode SerDes:

  • a bit-error rate test (BERT) must examine only the delimiter and the payload, and calculate bit-error rate. The sync pattern shouldn’t be taken into account.
  • SerDes must keep the same latency for every burst -- or, the BERT must have the ability to allow latency difference between bursts.

Anritsu says its MP1800A’s Pulse Pattern Generator (PPG) and Error Detector (ED) easily and accurately calculate the bit-error rate. Meanwhile, the CTXL1’s built-in self-test function can successfully align the latency on every burst, so the BERT is not required to compensate for the variation of the latency between bursts, K-Micro says. As a result, it was possible to measure burst mode lock time at 10.3125 Gbps with a BER of better than 1.0E-12.

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