Anritsu enhances MP1900A BER test capabilities for 400GbE transceiver, DSP verification

Anritsu Co. has added four capabilities to its Signal Quality Analyzer-R MP1900A BERT to enhance its applicability to PAM4-based 400 Gigabit Ethernet (400GbE) requirements. The features include multichannel synchronization, multilane forward error correction (FEC) pattern generation for 400GbE, inter-symbol interference (ISI) stressed signal generation to simulate transmission path losses, and application software for capturing error counts for the device under test. The enhancements should benefit technicians who need to evaluate the bit error rate (BER) of 400GbE transceivers and devices, as well as PAM4 digital signal processors (DSPs), the company says.

Mar 14th, 2019

Anritsu Co. has added four capabilities to its Signal Quality Analyzer-R MP1900A BERT to enhance its applicability to PAM4-based 400 Gigabit Ethernet (400GbE) requirements. The features include multichannel synchronization, multilane forward error correction (FEC) pattern generation for 400GbE, inter-symbol interference (ISI) stressed signal generation to simulate transmission path losses, and application software for capturing error counts for the device under test. The enhancements should benefit technicians who need to evaluate the bit error rate (BER) of 400GbE transceivers and devices, as well as PAM4 digital signal processors (DSPs), the company says.

The enhanced functionality resides in the MP1900A’s PAM4 pulse pattern generator (PPG). The upgrade makes the instrument of further use in 400GbE transceiver PHY layer FEC tests, as well as QSFP-DD and OSFP evaluations. The system also can conduct legacy jitter tolerance and input sensitivity measurements, as well as tests on the impact of crosstalk due to use of multiple channels and error correction. The PAM4 PPG also now offers a function for simulating signals after transmission through a PC board. The capability obviates the need to prototype multiple PC boards to test transmission path losses, while the ISI function improves testing efficiency.

Another built-in function, this one for communicating with the IC error-check function of the device under test, is also new. The enhancement simplifies jitter tolerance measurements during early stage development of high-speed devices, Anritsu says.

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