25 August 2003 San Jose, CA Lightwave -- Altera today announced interoperability between its Stratix GX field-programmable gate arrays (FPGAs) and PMC-Sierra's XENON family of OC-192, 10 Gigabit Ethernet (GE), and high density GE devices--ideal for advanced metro area networking equipment such as Ethernet switches and routers. The embedded dynamic-phase-alignment (DPA) capability featured in Altera's Stratix GX devices enables accelerated data transfer and frees valuable logic resources for other tasks. By leveraging the combined capabilities of the Stratix GX and XENON devices, system engineers can develop high-performance networking designs that meet specific customer requirements more rapidly and cost-effectively.
"Altera's POS-PHY Level 4 MegaCore function offers our customers a complete and reusable PL4/SPI 4.2 [POS-PHY Level 4/System Packet Interface Level 4 Phase 2] solution for multi-channel applications, where packet reassembly is a requirement," said Jean Lamarche, director of marketing and applications, Service Provider Division at PMC-Sierra. "As we have demonstrated with the XENON family, the DPA featured in Altera's Stratix GX devices greatly reduces the constraints on placement of components, as well as the layout effort required to route the 11-Gbit/sec bus between components."
PL4/SPI 4.2 is a source-synchronous interface protocol used for packet or cell transfers between physical and link layer devices at 10-Gbit/sec data rates and beyond, including 10 GE and high density GE. Designers can also use PL4/SPI 4.2 to connect two link-layer devices such as an FPGA and a network processor. The Stratix GX device includes a fully Optical Internetworking Forum SPI 4.2-compliant POS-PHY Level 4 MegaCore logic function with embedded DPA to provide the reliability required to ease board design.
Interoperability tests were conducted using a Tyco HM-Zd connector for Altera's Stratix GX board and a Molex 74057-1001 connector for PMC-Sierra's XENON board. The boards were connected via an interposer card capable of handling both connectors. Total trace lengths were 6 inches -- 3 inches from each device to its respective connector, and one channel length was deliberately extended to introduce approximately 0.3 UI of skew to test the Stratix GX device's reliability and robustness across process, voltage, and temperature variances. Testing was conducted using PMC-Sierra's XENON family of devices: PM3388 S/UNI 10xGE, PM5390 S/UNI 9953, PM3392 S/UNI 1x10GE, and PM3393 S/UNI 1x10GE-XP.
"PMC-Sierra authored the original POS-PHY Level 4 specification that evolved into the SPI 4.2 standard," said Tim Colleran, Altera's vice president of product marketing. "Demonstrating interoperability with their XENON family further validates the ability of our Stratix GX device, with its embedded data phase alignment, to support advanced telecommunication and other networking designs using the SPI 4.2 protocol."
Embedding the DPA feature in the silicon's source-synchronous channels, as opposed to a software approach, reduces skew and enables higher speed data transmission up to 1 Gbit/sec. A soft DPA implementation is slower, ties up valuable device logic resources and global clocks, and can be error-prone in the face of temperature or voltage changes.
The Stratix GX family is Altera's second-generation embedded transceiver family based on a 0.13-micron process technology with 1.5V core voltage. Stratix GX devised the 10-Gbit/sec PL4 system interface to terminate traffic running over 10 GE WAN, 10 GE LAN, 10-port GE, OC-192c ATM/packet over SONET (POS) and four-channel OC 48-c ATM/POS links.
The XENON devices enable customers to quickly and easily create a family of line cards by leveraging the design re-use within the devices. The recent addition of the PM3393 S/UNI 1x10GE XP device with integrated XAUI further enhances the flexibility of the XENON family by enabling customers to create line cards with pluggable optics such as XENPAK, XPAK, and X2 multi-source agreement. All XENON devices are currently in mass production.