Neralink secures a $1.6 million contract for its metro Ethernet intellectual property program

March 15, 2004 Lod, Israel--Neralink Networks, Ltd., announced a major milestone in a $1.6 million contract for the development of a RAM-based network processor based on the company's metro Ethernet intellectual property, including switch engine, metro Ethernet forum compliance policing, queue and traffic manager and ingress/egress header processor.

March 15, 2004 Lod, Israel--Neralink Networks, Ltd., announced a major milestone in a $1.6 million contract for the development of a RAM-based network processor based on the company's metro Ethernet intellectual property, including switch engine, metro Ethernet forum compliance policing, queue and traffic manager and ingress/egress header processor. Neralink received this project four months ago and has already demonstrated the functionality on a field-programmable gate array (FPGA) board.

Neralink's metro Ethernet intellectual property (MEIP)program, enables system vendors to use FPGA solutions as an alternative for expensive network processors and gain the flexibility of using FPGA as a wire-speed configurable hardware-based solution for the telecom networking market. In addition, this program is an effort designed to remove the cost and resource barriers for components vendors seeking to introduce new functionalities and technology for the metro and last mile Ethernet markets.

The MEIP arms metro Ethernet equipment and components vendors with a comprehensive set of IP cores of Verilog/VHDL source code, test benches, test plans, software, firmware, and system functionality to enable companies to reduce their costs and introduce new functionality and products. Neralink's VHDL/ Verilog FPGA/ASIC cores, include telecom Ethernet switch engine (TESE) at 24 Gbits/sec, traffic manager and scheduler with up to 256 queues, metro Ethernet forum traffic engineering compliance policing, 1024 connection AAL5 SAR for 1 Gbit/sec, DDR, MAC, GMAC and SPI-4. Neralink guides participants in the program throughout the development process, with system specifications, design guides up to full turnkey projects.

Neralink's TESE includes wirespeed 24-Gbit/sec switching for unlimited virtual ports, hardware MAC learning per user/VLAN/port, metro Ethernet forum services such as VPHS, VPWS, and VPLS. The ingress header processor can handle any header format such as GFP, PPP, Martini, MPLS, VLAN, QTAG, Q-in-Q and even ATM cells. The traffic manager and scheduler supports up to 256 queues and can be adapted to support more queues. Metro Ethernet forum compliance policing supports up to 2000 user/network streams, with unique integration with RED/WRED schemes.

"With this technology in our hands Neralink is in the forefront of telecom networking technology and on the way to releasing off-the-shelf RAM-based system on an FPGA solution for the metro access market," stated David Levi, founder and chief executive of Neralink. "By continued strong demand for Neralink Technology, IP and system design knowledge, the company is now under a massive investment round that will let the company leverage its current technology and become the leader in facilitating telecom networking technology."

Neralink's RAM-based metro Ethernet system on FPGA/ASIC intellectual property, available system products and modules can provide the right answers for OEM companies, from specification of an IP core up to complete turnkey designs, and off-the-shelf system products. Neralink will exhibit at Cebit, March 18-24 in Hall 13, booth #A34.

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