Fujitsu develops first CMOS selector chip operating at 50 Gbits/sec

March 23, 2004 Tokyo--Fujitsu Laboratories Ltd. and Fujitsu Ltd. today announced the development of a selector chip using CMOS technology capable of record-breaking 50-Gbit/sec throughput.

Mar 23rd, 2004

March 23, 2004 Tokyo--Fujitsu Laboratories Ltd. and Fujitsu Ltd. today announced the development of a selector chip using CMOS technology capable of record-breaking 50-Gbit/sec throughput. The new technology delivers the benefits of a highly integrated, low power design in CMOS with the 40-Gbit/sec performance levels required for devices used in high-bandwidth data communications, speeds that previously could only be attained using silicon-germanium chips or other compound semiconductors.

A selector chip is an integrated circuit that can select one output signal from multiple input signals. For example, a 2:1 selector chip takes a clock signal to alternately select between two data channels, multiplexing the input channels together into an output channel at double the speed.

This technology represents a breakthrough in achieving the 40-Gbit/sec throughput levels required of devices for next-generation telecommunications. Details of the new technology were presented last month at the International Solid-State Circuit Conference.

With the ongoing spread of broadband Internet access, there is a growing need for networks that can deliver higher speeds and bandwidth capacity. Although the current standard is 10-Gbit/sec, next-generation network systems need to be able to run at 40 Gbits/sec. Reaching those speeds will require ultra-fast chips that can process data at rates of at least 40 Gbits/sec, and most development work has focused on silicon-germanium and other compound semiconductors that offer superior speed characteristics.

But while devices using silicon-germanium or other compound semiconductors can offer superior speed, they consume very high levels of power, posing heat problems for highly integrated designs, and are expensive in terms of manufacturing costs. CMOS chips, on the other hand, consume less energy and cost less, but the transistor characteristics and interconnect parasitic capacitances of CMOS chips have--with the approaches pursued up until now--made it difficult achieve speeds exceeding 40 Gbits/sec.

This new technology enables CMOS circuits to operate faster. With a new circuit schematic employing inductors and cutting-edge 90-nm CMOS technology, Fujitsu was able to achieve a dramatic increase in processor throughput. An inductor is an element in a circuit that grows more resistant to electricity as frequencies grow higher. It is usually used in semiconductors in a spiral-wiring pattern. The key features of the new technology are as follows:

Inductor peaking. To eliminate the factors within the circuit relating to transistors and interconnect parasitic capacitances that inhibit high-speed operation, Fujitsu placed an inductor at an optimized location on each circuit, achieving a breakthrough in operating speed. The inductor is a 3-micron copper trace formed on the top interconnect layer.

Advanced 90-nm CMOS technology. Building on the current generational standard of 90-nm CMOS technology, Fujitsu used transistors with a reduced gate length of 48 nm and optimized the circuit parameters to maximize the chip performance.

Highly precise modeling. Fujitsu developed a modeling methodology that, across the range from low-frequency operation to high-frequency, precisely corresponds to each element of the circuit, including the transistor, inductor, and interconnect. This methodology enabled highly precise circuit simulation, resulting in an optimized circuit design even with the inclusion of the novel inductor circuit structure.

Fujitsu developed two selector chips with different circuit schematics using this technology, achieving throughput of 43 Gbits/sec and 50 Gbits/sec, respectively. This is the first time that chips using CMOS technology have verifiably achieved operating speeds in excess of 40 Gbits/sec.

The selector chip operating at 50 Gbits/sec uses a circuit schematic that takes 1.0V power, standard for 90-nm CMOS chips, and would be relatively easy to develop into large-scale system-on-chip devices.

Fujitsu is currently developing large-scale system-on-chip devices incorporating this technology, aiming for commercial release some time around 2006 to 2007.


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