Phyworks launches Advanced FEC core
April 19, 2004 Bristol, UK--Following the recent approval of ITU recommendation G.975.1, Phyworks announces the availability of its Advanced FEC implementation as a silicon IP core.
April 19, 2004 Bristol, UK--Following the recent approval of ITU recommendation G.975.1, Phyworks announces the availability of its Advanced FEC implementation as a silicon IP core. This development enables the integration of its Advanced FEC into third-party components and the new generation of system-on-chip devices, which will combine framers, FEC and other physical-layer functions. Using Advanced FEC core, component vendors will be able to keep the same software interface and chip footprint as existing solutions.
Advanced FEC has a net electrical coding gain of 9.4 dB at the industry standard 6.69% overhead and is the first commercial implementation optimized to take advantage of soft decision information, according to Phyworks. The algorithm lends itself to extremely efficient silicon implementation with low power consumption, less than 2W for a 10-Gbit/sec implementation in 0.13-mm CMOS technology, and small chip area. The Advanced FEC intellectual property is protected by a portfolio of patent applications covering both the algorithm and silicon implementation. Phyworks also supplies 10-Gbit/sec transceiver chips which provide soft decision information.
"We have put two years of research and development effort into the development of our Advanced FEC algorithm and design," said Allard van der Horst, product manager at Phyworks. "The inclusion of our FEC algorithm in the new ITU standard sends out a strong message to our customers that we lead the way with our designs, helping to set industry standards and offering market-beating performance."