Cypress and Xilinx accelerate deployment of next-gen data over SONET/SDH for metro applications
8 August 2003 San Jose, CA lightwave Europe -- Cypress Semiconductor Corp and Xilinx, Inc have announced the collaborative co-development of reference designs for next generation communications and memory products.
The first product resulting from the relationship (through the Xilinx Reference Design Alliance Program) is a reference design for implementing a complete "fibre-to-fibre" data over SONET/SDH solution. Further designs targeting packet-processing applications are currently under development.
The design, which uses transparent generic framing procedure (GFP-T) for data encapsulation and virtual concatenation for optimal bandwidth utilisation, deploys two client channels over SONET, each independently configurable for multi-protocol standards, including any combination of Gigabit Ethernet, Fibre Channel, ESCON, and FICON.
By leveraging Cypress's MetroLink2T-2TM core to implement GFP-T functions, the reference design is optimised for the Xilinx Virtex-IITM FPGA. Cypress believes its MetroLink core is the first Link Layer Device on the market to offer GFP-T. The Virtex-II device uses flexible SelectI/O-Ultra technology to interface seamlessly to Cypress's POSIC2GVC SONET/SDH framer and HOTLink II serialiser/deserialiser.
"Using the Virtex-II device to implement the MetroLink2T-2 link-layer function enabled us to provide our customers with a complete metro-transport solution quickly and with little risk as their requirements evolve throughout the design cycle," says Geoff Charubin, director of marketing for Cypress's Data Communications Division.
"Using this reference design, MSPP and DWDM manufacturers can quickly bring a GFP-T platform to market, allowing their system architects to focus on higher-layer functions within their system and differentiating their solution from the competition."
Jerry Banks, director of Partnerships and Alliance marketing at Xilinx, says, "We are pleased to work with Cypress to further demonstrate the capability of our Virtex-II FPGAs in advanced packet processing solutions. This joint reference platform includes the Cypress MetroLink LLD core implemented on the Xilinx Virtex-II FPGA and enables communication system designers to bring 'SONET over any protocol' to market more quickly."
As part of the interoperability testing, critical interface timing between the POSIC2GVC framer, the HOTLink II SERDES and the FPGA have been completed and verified a complete reference design with application note, including Verilog and VHDL code, is included to speed time-to-market.
Cypress's participation in the Xilinx Reference Design Alliance Program means the companies will jointly market the reference design board, cross-reference their application notes and product data sheets on each other's web sites, and provide layout guidelines and board schematics.