Applied Micro Circuits Corp. (AMCC) introduced the S3065 and the S3465 devices. The S3065 and S3465 are CMOS multi-rate transceivers with integrated Clock and Data Recovery (CDR), and offer jitter generation performance.
According to the company, the S3065 is the only available CMOS 16-bit multi-rate OC-48 transceiver with CDR and features a 16-bit differential LVPECL interface. The S3465 is a CMOS OC-48 multi-rate transceiver with CDR and features a 4-bit LVDS interface. Both devices perform clock and data recovery, and serializer/deserializer functions for OC-3/12/24/48 (with or without FEC), Fibre Channel, 2 x Fibre Channel, HDTV, and Gigabit Ethernet. The S3065 and S3465 build upon the advanced features of AMCC's S3055 and S3455 OC-48 transceivers, which began shipping in high volume earlier this year.
The second-generation transceivers couple jitter generation performance with low power and low cost to provide a complete end-to-end multi-rate solution that meet the requirements of new intelligent optical networking equipment. Exceeding Bellcore and ITU-T specifications, each device features a jitter generation of 5mUI rms, providing outstanding design margin for SONET applications. The S3065 and S3465 are designed for use in SONET/SDH/ATM-based transmission systems and Wavelength Division Multiplexing (WDM) equipment.
The S3065 is footprint compatible with the S3055 and was designed with a 16-bit differential LVPECL data path to interface with AMCC's framers including Amazon, Missouri, Rhine, and Indus. With a 4-bit LVDS interface, the S3465 was designed from its inception to work seamlessly with AMCC's framers including Ganges, Danube, and Ohio. In addition, the S3465 is footprint compatible with AMCC's S3455 transceiver, which allows for easy migration between devices.
Both devices provide diagnostic loopback (transmitter-to-receiver) and line timing (receiver-to-transmitter) modes. The S3065/S3465 also incorporate an internal FIFO (first in, first out) to decouple transmit clocks and an on-chip high frequency phase-locked loop (PLL) for clock generation. The PLL on-chip clock synthesis function enables the utilization of a slower external transmit clock reference. The reference clock features a frequency of 155.52 MHz, in support of existing clock schemes, and supports other reference clock rates appropriate for FEC and non-SONET data rates. The devices perform all necessary serial-to-parallel and parallel-to-serial conversions. The S3065 utilizes dual 1.8/3.3 V supplies, offers an industry standard differential LVPECL interface, and typical power consumption of 1.25W. The S3465 utilizes a single 1.8 V power supply, interfaces with LVDS and LVCMOS logic, and features power consumption of less than 900mW.
Both products are currently in volume production. Evaluation boards are also available. The S3065, available in a packaged 324-pin PBGA, is priced at $64 in quantities of 100,000. The S3465, available in a packaged 196-pin FC-PBGA, is priced at $43 in quantities of 100,000.
About AMCC:
AMCC designs, develops, manufactures, and markets high-performance, high-bandwidth silicon solutions for optical networks. For more information, visit www.amcc.com.