100G chips slowly get up to speed
By Stephen Hardy
Advances must be made across an entire technical ecosystem before standards-based 100-Gbps transmission becomes a reality. That includes the ICs that will appear inside or next to optical modules.
Semiconductors may not be the first thing that comes to mind when considering 100 Gbps. Yet the role electronics plays in optical communications grows as the demands on fiber-optic systems increase. Regardless of what may be top of mind at 100 Gbps, semiconductor development may prove the gating factor that determines when 100-Gbps technology can meet user requirements, both technical and economic.
The chips of interest to optical transceiver and transponder designers can be roughly divided in half–those that reside inside the module and those on the board that interface with the module. The fact that functions frequently move from inside the module to the chips on the board reinforces this twin focus.
The developers of the 40- and 100-Gigabit Ethernet (GbE) specifications that fall within the scope of the IEEE P802.3ba Task Force had such functional migrations in mind when they began work, according to John D’Ambrosia of Force10 Networks (www.force10networks.com), who chairs the task force.
“If you look back at the 10-gig optics, what initially came out of the group was more complicated than desirable, because most of the interfaces were XAUI based and you basically wound up having several layers that you put into your optics solution–which quickly evolved to ‘take all that stuff out.’ And now we have simple solutions like the XFP or SFP” says Ambrosia.
So the task force has focused on simplicity within its architecture. It has also sought flexibility, a necessary requirement for a scheme that must accommodate 40 and 100 Gbps in various incarnations.
The architecture as currently envisioned contains several layers. (The Ethernet Alliance offers a whitepaper on its site that explains how each of these layers work.) The key ingredient, according to D’Ambrosia, is the Multi-Lane Distribution (MLD) scheme employed for the physical coding sublayer (PCS). MLD enables the architecture to accommodate a variety of physical medium dependent (PMD) approaches–ranging from 4×10 Gbps for 40GbE to 10×10 Gbps, 4×25 Gbps, 2×50 Gbps, and 1×100 Gbps–by having the physical medium attachment (PMA) layer multiplex together the appropriate number of lanes. At 100 Gbps, there will be 20 PCS lanes; they support interface widths of 1, 2, 4, 5, 10, and 20 channels or wavelengths. Chip developers often refer to the device that will perform this function as a “gearbox.”
In keeping with the goal of simplicity, the task force has stayed away from serial transmission at 100 Gbps. (It had done the same with 40 Gbps, but the Ethernet Alliance recently launched an incubator effort for a serial approach to 40GbE.) The modules will feature either parallel arrays or WDM transmission of either 10- or 25-Gbps data rates (actual bit transmission will be somewhat higher due to coding overhead). The hope is to leverage previous work in 10 Gbps and, in the case of the 25-Gbps transmissions, serial 40 Gbps.
D’Ambrosia believes that the architecture will indeed bring simplicity and flexibility to 40GbE and 100GbE. But that doesn’t mean chip designers have no work to do. New MACs and PHYs must be developed–and, as usual, product designers want to see them ahead of the standard’s ratification.
While D’Ambrosia anticipates the standard will achieve ratification on schedule, that milestone isn’t slated until June 2010. What kind of guidance do the specs in their current form provide chip developers? Theorizes D’Ambrosia, “Obviously, some things may change to some degree. But I think they have a very good idea of where they need to be.”
Some chip developers appear to agree. At OFC/NFOEC in March, NetLogic Microsystems (www.netlogicmicro.com) demonstrated its NLP10142 100GbE PHY. According to Siddharth Sheth, director of marketing, physical layer products at NetLogic Microsystems, the PHY is sampling to “quite a few” customers, which has led to five design wins at Tier 1 customers, mostly core router and aggregation switch vendors.
Yet the complexity of the task silicon vendors face should not be minimized. Jim Theodoras, director, technical marketing at system house ADVA Optical Networking (www.advaoptical.com), notes that the semiconductor community will face an expensive design process and probably limited market demand, at least initially. “In many cases, the PHY will be split into separate chips or physical locations,” he wrote in an e-mail. “So, in summary, a 100GbE chipset will be made up of 3–4 complex, expensive ICs, each costing millions per fabrication.”
Nevertheless, D’Ambrosia is heartened by the work he’s seen as well as the development of module multisource agreements such as the CFP. “There’s nothing that I can say to you I’m nervous about at this point,” he says. “It’s just doing the work; it’s not doing the groundbreaking work.”
Developers of serial 100-Gbps technology are breaking new ground, however. The Optical Internetworking Forum (OIF) has attempted to concentrate these efforts in one spot: dual-polarized quadrature phase-shift keying (DP-QPSK) as a modulation format, with coherent detection as a boost.
While some system vendors have struck out on their own in regard to 100-Gbps modulation schemes, much of the chip development has focused on the work of the OIF. Thus, silicon companies have two problems to help solve: creating the modulated signal and then receiving and demodulating it.
Most agree that the interfaces from the board to the 100-Gbps module will leverage the work of the IEEE P802.3ba Task Force. However, that means multiple data streams coming into the module that have to be multiplexed to 100 Gbps.
Silicon vendors are already on the case. For example, Sierra Monolithics Inc. (www.monolithics.com) unveiled its Theta-100G devices, which include the SMI10021 10:4 mux/CMU and SMI10031 4:10 CDR/demux devices, at OFC/NFOEC. The chipset operates at 4×25 to 28.3 Gbps (although will likely have to go faster, as the OIF subsequently increased the FEC rate to 32 Gbps) and incorporates an integrated DP-DQPSK modulation precoder function. They were slated to begin sampling this quarter.
Once through the multiplexer, the signals must pass through a modulator driver. “The speed is not an issue,” according to Niall Robinson, vice president of product marketing at Mintera (www.mintera.com), of DP-QPSK modulator drivers. “The problem is you need four of them [because QPSK transmits in four phases]. So you would like to see some integration there. Otherwise, the solution is going to be quite large.”
Again, chip vendors have stepped up. GigOptix (www.gigoptix.com) is developing a four-channel Mach-Zehnder (MZ) modulator driver, initially integrated into a single GPPO package. The target release for production samples is Q1 2010; however, company director of product marketing Padraig O’Mathuna confirms that early prototypes have reached potential customers. Meanwhile, Triquint Semiconductor (www.triquint.com) and Inphi Corp. (www.inphi-corp.com) have also released drivers for this application as well.
However, the real challenge comes on the receive end. In particular, the analog-to-digital converters (ADCs) and digital signal processors (DSPs) will stretch the bounds of what’s on the market today. For example, each of the four incoming data streams in DP-QPSK will need an ADC capable of at least 60 Gsamples/s. Meanwhile, the DSP may have to deal with 1.2 Tbits of information.
Fujitsu Microelectronics Europe (www.fujitsu.com/emea/services/microelectronics/) has announced the development of a 56-Gsamples/sec ADC. “The trick, of course, is can they package four of those A/D converters with the DSPs and come up with a single-chip solution,” says Robinson. “You won’t have two separate ASICs on a PCB because you’ve got 1.2 Tbits of information. Really, you need those A-to-D converters right up next to the DSP to keep the tracks as short as possible.”
The trick for module vendors–as well as system houses who sense a near-term market opportunity–is whether to wait for the merchant market to meet their needs or come up with something in-house. Ciena Corp. (www.ciena.com) used in-house ASIC technology for its new 100-Gbps offering, while ADVA Optical Networking has embraced an alternative to DP-QPSK, differential phase-shift keying, three-level amplitude-shift keying, in the absence of off-the-shelf DP-QPSK technology.
Thus, silicon vendors looking to make a mark at 100 Gbps, particularly in serial applications, will face technical hurdles as well as customers whose patience may prove shorter than silicon development cycles.
Stephen Hardy is editorial director and associate publisher of Lightwave.
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