Fujitsu Semiconductor Europe offers four-channel 65-GSa/s DAC

Fujitsu Semiconductor Europe has launched a partner for its CHAIS ADC for 100-Gbps coherent receivers. The new 8-bit, four-channel DAC leverages 40-nm CMOS technology and provides a sampling rate range of 55 to 65 GSa/s per channel at a power dissipation of 0.75 W per channel.

Using standard CMOS for both converters opens the door to integrating them on a single die together with a complex DSP and high-speed serial OTN framer interfaces to form a 100-Gbps DP-QPSK transceiver, Fujitsu Semiconductor Europe asserts. The 2 Tbps of data that would be converted with four channels running at 65 GSa/s would in fact demand such an integrated approach, the company concludes.

The use of DACs offers several advantages over standard digital interfaces, Fujitsu Semiconductor Europe continues. Managing skew among the four signal component lanes in the digital domain enables stable control across processing, temperature, or voltage variations in the transceiver. Meanwhile, signal processing in the digital domain enables compensation of non-linearities in the transmit optics chain and mitigation of signal reflections at the device IOs. Integrating the four-channel DAC into the transceiver also removes the requirement for a separate multiplexer/encoder device.

Said Manfred Mettendorff, director of the Communications Business Unit at the company, “This effort not only underpins refinements in the current generation of 100-Gbps systems, such as broader feature sets and power optimisations for smaller form factors, but will also enable 400-Gbps transport rates and beyond.”

A development kit for the 65-GSa/s DAC will be available from November 2011. Development kits for the 65-GSa/s CHAIS ADC are currently available.

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