FPGA vendor Xilinx Inc. (Nasdaq: XLNX) announced it has acquired Modelware, a provider of traffic management/packet processing silicon intellectual property (IP) cores. Simultaneously, Xilinx unveiled FPGA-based 100-Gbps traffic management reference designs based on its Virtex-6 HTX FPGA.
Gilles Garcia, director of Xilinx’s Wired Communication Business Unit, told Lightwave last Friday that he expects the newly acquired capabilities to prove useful in equipment designs aimed at mobile backhaul, PON aggregation, and data center applications. In particular, he sees packet-optical transport systems as a natural for the Modelware IP.
The new reference designs will be available in June. However, Garcia reports that several customers have already used the Modelware IP in combination with Xilinx FPGAs prior to the acquisition.
The IP cores can process 150 million packets-per-second with 64B packet size on a single FPGA. The Modelware cores also will support protocols such as HDLC, ATM, and PWE3.
"By delivering a highly integrated solution encompassing packet processing/traffic management and an array of connectivity IP cores, together with their reference design, Xilinx is addressing the critical time to market and total cost of ownership requirements of equipment makers gearing up for the high bandwidth-granular services roll-outs underway by service providers, enterprise, and data center operators," said Matthias Machowinski of Infonetics Research.
The Modelware acquisition furthers Xilinx’s “one-stop shop” strategy for support of FPGA-based high-speed network designs. The company earlier added OTN capability through the acquisition of Omiino (see “New Virtex-6 capabilities, Omiino acquisition point Xilinx toward 400G OTN FPGA support”).
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