Avago demos CEI-25G-LR compliant SerDes in 28-nm

Avago Technologies (Nasdaq: AVGO) says its 25-Gbps Serializer/Deserializer (SerDes) core in 28-nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR). The CEI-25G-LR compliance makes the chip a natural choice for 100-Gigabit Ethernet (100GbE) equipment design applications.

Avago Technologies (Nasdaq: AVGO) says its 25-Gbps Serializer/Deserializer (SerDes) core in 28-nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR). The CEI-25G-LR compliance makes the chip a natural choice for 100-Gigabit Ethernet (100GbE) equipment design applications.

The company will demonstrate the 25G SerDes cores in backplane applications at the DesignCon 2012 exhibition from January 31 to February 1. The embedded SerDes cores are often integrated in ASICs within equipment designs for networking, computing, and storage applications.

“This compliance is not only another first for our SerDes cores, but it marks a significant step forward in the march to 100G Ethernet Infrastructure,” said Frank Ostojic, vice president and general manager of the ASIC Products Division at Avago. “As part of the push toward 100G, Avago is planning to use our 25G SerDes as the basis for future standard products. Capable of driving 5 meters of copper cabling at low power, the 25G SerDes is suitable for a range of applications and is now available to a larger group of customers.”

Avago says it has integrated more than 400 SerDes channels on a single ASIC. The 28-nm Avago SerDes cores feature a “unique” decision feedback equalization (DFE) architecture. This DFE architecture results in low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance, Avago asserts.

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