Credo says it now offers the 3.2-Tbps BlueJay retimer chiplet, designed to support 64 lanes of 56-Gbps PAM4 LR DSP connectivity. The BlueJay chiplet targets multi-chip-module (MCM) ASICs used in advanced switching, high-performance computing, artificial intelligence (AI), and machine learning applications.
The retimer chiplet communicates with the MCM system-on-chip (SoC) core on the host side using what Credo asserts is an ultra-low-power Bunch of Wires (BoW) die-to-die interface. The wide-bus BoW interface is optimized for the TSMC CoWoS packaging technology for high-performance computing applications. On the line side, the chiplet supports 64 lanes of 56G PAM4 LR SerDes that Credo says enables smooth integration in various system-level configurations. The SerDes designed enables the BlueJay chiplet to be manufactured in TSMC's 28-nm process, Credo adds.
Use of the chiplet approach, which moves the SerDes off-chip, frees as much as 30% of ASIC die area for other functions, such as additional compute, increased switching performance, and deeper routing tables. “Integrating chiplets allows our customers to accelerate ASIC designs with increased performance to support advanced switching, storage, high-performance computing, AI, machine learning, and service provider applications. These data-intensive applications place a wide range of architectural demands on next-generation ASICs,” said Michael Girvan Lampe, vice president of worldwide sales at Credo.
“Networking and data center architectures are transitioning their infrastructure from 400 Gbps to 800 Gbps and beyond, requiring higher-performance, lower-power ASICs that combine digital core and analog interface functionality,” commented Alan Weckel, founder and technology analyst at 650 Group, via a Credo press release. “However, achieving performance in a monolithic ASIC component is challenging since analog and digital process nodes advance at different rates. Multi-chip modules using Credo’s retimer chiplets decouple the analog interface from the digital core ASIC, reducing costs, lowering risk, and enabling the accelerated transition cycle.”
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