Marvell (NASDAQ: MRVL) says it now offers what it asserts is the first 112G SerDes based on 5-nm processes. The company says that the SerDes has been validated in hardware and is at the center of a new custom ASIC design win in which Marvell’s customer will embed the 5-nm SerDes IP to build top-of-rack (ToR) and spine switches.
The 112G 5-nm SerDes supports 112G PAM4 across channels with >40-dB insertion loss, along with power reduction of more than 25% compared to 7-nm alternatives, making it applicable to systems with tight thermal/power constraints while reducing cost. These characteristics will make the SerDes particularly useful in support of constrained 5G applications, Marvell states.
“Our new 112G 5-nm SerDes solution, with its industry-leading power, performance, and area metrics, is a true game changer and will help scale data infrastructure to meet growing interconnect requirements,” asserted Sandeep Bharathi, senior vice president of Central Engineering at Marvell. “System performance is typically limited by bandwidth and power in most infrastructure applications, and our new 112G solution in 5 nm addresses this by doubling the bandwidth, while reducing the overall I/O power.”
“Marvell is clearly staking out a leadership position as the market rapidly transitions to 100G serial,” commented Alan Weckel, founder and technology analyst of 650 Group, via a Marvell press release. “We expect that 100G serial will be a foundational speed similar to 10G and 25G, and an important technology in enabling the evolution of data center architectures optimized for emerging workloads such as AI and machine learning. By bringing this 112G 5-nm SerDes solution to the industry now, Marvell is accelerating the deployment of next generation infrastructure and raising the bar on performance capabilities across compute, networking, and storage.”
The 112G SerDes is part of what Marvell promises to be Marvell a suite of PHYs, switches, data processor units (DPUs), custom server processors, controllers, accelerators, and custom ASICs in 5 nm (see "Marvell, TSMC partner on 5-nm wafer production").
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Stephen Hardy | Editorial Director and Associate Publisher, Lightwave
Stephen Hardy is editorial director and associate publisher of Lightwave and Broadband Technology Report, part of the Lighting & Technology Group at Endeavor Business Media. Stephen is responsible for establishing and executing editorial strategy across the both brands’ websites, email newsletters, events, and other information products. He has covered the fiber-optics space for more than 20 years, and communications and technology for more than 35 years. During his tenure, Lightwave has received awards from Folio: and the American Society of Business Press Editors (ASBPE) for editorial excellence. Prior to joining Lightwave in 1997, Stephen worked for Telecommunications magazine and the Journal of Electronic Defense.
Stephen has moderated panels at numerous events, including the Optica Executive Forum, ECOC, and SCTE Cable-Tec Expo. He also is program director for the Lightwave Innovation Reviews and the Diamond Technology Reviews.
He has written numerous articles in all aspects of optical communications and fiber-optic networks, including fiber to the home (FTTH), PON, optical components, DWDM, fiber cables, packet optical transport, optical transceivers, lasers, fiber optic testing, and more.
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