March 11, 2005 Menlo Park, CA -- SyntheSys Research has introduced an integrated stressed eye generator option for its BERTScope analyzer family. The company says the option allows the analyzer to overlay controlled levels of jitter, as well as an adjustable sinusoidal interference signal, on top of data patterns for compliance testing of receivers.

High-speed interfaces such as 4-Gbit/sec Fibre Channel, second- and third generation Serial-ATA, Serial Attached SCSI, Fully Buffered DIMM, SONET, SDH, 10 Gigabit Ethernet, and 11 Gbit/sec OIF-CEI require verification of compliance with input jitter tolerance levels. According to the company, within a single instrument, its analyzers combine eye diagram analysis, jitter analysis, and bit error ratio test (BERT) pattern generation and error analysis.

According to the company, the stressed eye option is created by adding programmable sinusoidal, deterministic, random, and bounded jitter to the analyzer's data pattern generator. For extra versatility, external inputs are provided to monitor user-generated stress. The company says that, with the option, stressed eye tests can now be flexibly controlled and generated, and that integrated generation of sinusoidal, random and bounded, uncorrelated jitter offers a calibrated output of automated measurements addressing multiple standards.

The option is priced at $19,500, and is available as an upgrade to existing analyzers. A second option, Physical Layer Analysis, is additionally required.