10-GbE PHY/SerDes ICs feature integrated clocking synthesizers, VCSEL drivers
January 30, 2006 Mountain View, CA -- Aeluros has announced the availability of its next-generation 10-Gigabit Ethernet (GbE) PHY/SerDes devices, which feature integrated clock synthesizers and VCSEL driver functionality. The company says the devices, available in pin compatible form, add to its 800mW Puma AEL1001/AEL1002 device family, providing a complete portfolio of 10 Gbit/sec-to-XAUI devices for optical module and line card applications.
According to the company, the Puma AEL1004, a WIS-enabled version of the Puma product family of 10-GbE PHY/SerDes devices, incorporates on-board clock synthesizers that eliminate the need for board designers to provide two clock sources for Ethernet and SONET/SDH rates. The company says that, with this patent-pending design approach, a single clock input of 155.52 MHz is sufficient to drive both the SONET/SDH and Ethernet/XAUI clocking requirements in the device. Additionally, on-board clean-up circuitry also allows the device to provide stratum-3 level line-timing capability for SONET/SDH timing requirements.
The Puma AEL1006 device is a next-generation LAN PHY device with integrated VCSEL driver functionality. Reference hardware that demonstrates this functionality in X2 optical modules is also available. This device also includes on-board clock synthesizer functionality that allows Ethernet/XAUI rates to be synthesized from a low-cost 50-MHz input, allowing further cost reduction in optical modules, according to the company.
