Marvell sampling Alaska C 5-nm 1.6-Tbps Ethernet PHY with 100G PAM4 I/Os

June 10, 2021
The company sees the retimer and gearbox PHY as a key building block for 100G serial-based 400G and 800G Ethernet optical modules.

Marvell (NASDAQ: MRVL) says it has begun sampling the 88X93160 Alaska C PHY, which it says is the first dual 1.6-Tbps Ethernet PHY with 100G PAM4 electrical input/outputs (I/Os) in 5 nm CMOS. The company sees the retimer and gearbox PHY as a key building block for 100G serial-based 400G and 800G Ethernet optical modules.

With the industry transitioning from 50G serial lanes to 100G, the doubling of the signaling rate has created signal integrity challenges that require power efficient retimer and gearboxes. The use of 5-nm CMOS meets this power efficiency need, says Marvell, as the 88X93160 Alaska C PHY will provide a 40% savings in I/O power compared to 50G PAM4-based alternatives.

The 1.6T PHY complies with IEEE 802.3ck for 100G serial I/Os and the Ethernet Technology Consortium’s 800GbE specifications. The device’s gearboxing capabilities enable switch ASICs with 100G serial I/Os to interface with existing 50G PAM4 based 400G optical modules. Meanwhile, the 88X93160 Alaska C PHY incorporates the company’s 112G 5-nm SerDes technology which enables operation at 112G PAM4 across channels with >40-dB insertion loss.

“100G serial electrical signaling is vitally important because it serves as the foundational speed for the next generation of high-speed networks,” said Alan Weckel, founder and technology analyst of 650 Group, via a Marvell press release. “Challenges in signal integrity typically arise as I/O speeds increase. As the industry transitions to 100G serial electrical signaling on high-density switches and optics, Marvell’s 1.6T PHY is the only solution that’s available in the market today to support this transition.”

“Data center demand for 400GbE and beyond is experiencing exponential growth,” added Achyut Shah, senior vice president and general manager of Marvell’s PHY business unit. “We are very proud to offer the industry’s first dual 1.6T PHY with 100G PAM4 I/Os designed for cloud data centers. Our 112G SerDes in 5 nm boasts industry-leading power and greatly enhances the value that high-speed Ethernet brings to cloud data center applications.”

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About the Author

Stephen Hardy | Editorial Director and Associate Publisher, Lightwave

Stephen Hardy is editorial director and associate publisher of Lightwave and Broadband Technology Report, part of the Lighting & Technology Group at Endeavor Business Media. Stephen is responsible for establishing and executing editorial strategy across the both brands’ websites, email newsletters, events, and other information products. He has covered the fiber-optics space for more than 20 years, and communications and technology for more than 35 years. During his tenure, Lightwave has received awards from Folio: and the American Society of Business Press Editors (ASBPE) for editorial excellence. Prior to joining Lightwave in 1997, Stephen worked for Telecommunications magazine and the Journal of Electronic Defense.

Stephen has moderated panels at numerous events, including the Optica Executive Forum, ECOC, and SCTE Cable-Tec Expo. He also is program director for the Lightwave Innovation Reviews and the Diamond Technology Reviews.

He has written numerous articles in all aspects of optical communications and fiber-optic networks, including fiber to the home (FTTH), PON, optical components, DWDM, fiber cables, packet optical transport, optical transceivers, lasers, fiber optic testing, and more.

You can connect with Stephen on LinkedIn as well as Twitter.

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